COMPUTER AIDED DESIGN: The commercial CAD tools are often not adequate for specific VLSI design applications and as such, the following software packages are being developed in BETA lab. and proved to be advantageous for their purposes.

o Silicon Compiler for Multirate Systems
o Analog Silicon Compiler
o Analog Layout Synthesizer
o Digital Test System Design
o Silicon Assembler for Booth Multipliers
o Waveform relaxation based MOS VLSI circuit simulator

DSP ARCHITECTURES: One of the applications in VLSI is for telecommunication applications. Namely, ASICs in the form of processors or codecs implementing a particular video coding or image compression algorithm are often the best solution. The following processors are implemented using a mixed bottom-up and top-down approach. A number of these processors are currently in the process of final verification, whereas the processors employing Wavelet transforms are ready for fabrication:

o Morphological Filters for Image Processing
o 2-Band Wavelet Decomposition and Synthesis Architectures
o M-Band Wavelet Decomposition and Synthesis Architectures
o Shuffled Block Transform Processor

DIGITAL BUILDING BLOCKS: Often it is necessary to design and characterize own bulding blocks for digital systems. In addition to processors, optimum design of critical data paths are one of the most important areas in VLSI. The following blocks are designed and charactarized for operation in Silicon. A number of these blocks are to be sent for prototype fabrication in two weeks.

o Bit Level Pipelined Parallel Multiplier
o Digit Serial Multiplier
o Radix 2n Multiplier
o Radix-2 Booth Encoded Multiplier

NEURAL NETWORKS: The VLSI design group has also specialized on the efficient design styles of Neural Networks which has become a choice in many industrial applications such as quality inspection, intelligent control and pattern recognition. Conventional implementations of neural networks include software running on computers or dedicated hardware. However, single chip implementations suffer from non-idealities within the circuit. Thus, novel strategies should be developed preferably in analog domain to resolve the application difficulties encountered in industrial applications. The following software packages are under development/developed for design automation of analog neural networks:

o ANNSiS: Analog Neural Network Simulation system for proper characterization of Neural ICs built based on analog modules.
o ANNSyS: Analog Neural Network Synthesis System including trainer system using ANNSiS which is capable of performing automatic layout synthesis.

The following work is also carried out for a complete design environment:

o Design and Implementation of Building Blocks for Multilayer Perceptrons: A test IC is fabricated using MIETEC 2m double poly CMOS technology. The aim is to characterize various floating gate transistors for weight storage. The IC is delivered and the characterization is underway. The preliminary results show prospect for the usage of floating gate transistors. In addition a special Op-Amp is also incorporated in this test chip which is a mixed signal design. The opamp is a novel design which is fully CMOS with a built-in bias generator with no external settings. The test results agreed very well with the expected results. Thus, in addition to its possible applications this type of Op-Amp will also constitute the building block of an Analog Neural Network as a neuron.

o I2C Bus Controlled Video Switch: This is an industrial design implemented in MIETEC's HBIMOS technology, offering an improvement and optimization in the TV systems. The design is ready for fabrication and to be sent to fabrication shortly.
o On Screen Display Unit: Another industrial design, to be manufactured in CMOS technology.

o ATM Switching Element: The next generation computer networks will employ the Asynchronous Transfer Mode of packet switching. The main goal here is to gain know-how in this filed. The current work is a joint effort with the Computer enginnering department, in the pursue of establishing a prototype ATM network. At this point an ASIC implementing a 2x2 switching of ATM packets is already developed in 1m ES2 technology and post layout simulations show a speed of 155 Mbits/sec, which is the ATM standard. The next step is to fabricate the IC and build a switching fabric to accomodate the ATM protocol.
o Switched Capacitor Filters for Wavelet Transforms: The digital implementations of Wavelet Transform consume a large silicon area, although they prove to be effective for speed. However, for less demanding applications, switched capacitor decimator/interpolator systems can be a better choice, thus consuming much less area. For this purpose, a design is under progress.

2007 Bogaziçi University