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Instructor:

             Assistant Professor Senol Mutlu

BETA Lab, Tel: (212) 359-7442

             e-mail address: senol.mutlu@boun.edu.tr

Office Hours:

At my office, by appointment. I have an open door policy.

Lectures:

TBA

Credits: (3+0+0) 3

Course Description:

Mastering the hardware description language, VHDL (Very high speed integrated circuits Hardware Description Language), for the design (specification, simulation, and synthesis) of digital systems and implementing them on FPGAs. Designing complete digital systems starting from the concept, advancing through the simulation, synthesis, and test, by using different styles in VHDL, namely structural, dataflow, and behavioral, for describing the architecture. Implementing designs on FPGAs (mainly Xilinx SpartanII).

 

Website:

http://www.cims.ee.boun.edu.tr

Your username is your student ID. Your initial password is also your student ID if this is the first time you are using it. Please change your password after the first time you logged in. Course info, some additional course material and your grades will be published on this website.

 

Prerequisites:

Digital design: gates, combinational and sequential circuits

Programming fundamentals

EE-140/CmpE-240: Digital design

Recommended: CmpE-344: Computer Organization or EE-443:Microprocessors

Textbook:

Reference textbooks:

Zainalabidin Navabi,VHDL: Analysis and Modeling of Digital Systems, McGraw-Hill Publishing, 1998, (BU Library: TK7874.N36 1993).

J.M. Rabaey, Digital Integrated Circuits, Pearson Education Inc.,2003.

 

CAD Assignments:

The purpose of CAD assignments is to build the components of a CPU or a microcontroller. With these developed components, it will be easier to work on the project.

Cad 1: Inverter/Nand/2:1 Mux/D Flip-Flop design and testing (Individual work)

Cad 2: Register File and ALU (Individual work)

Cad 3: Shifter and Program Counter (PC) (Individual work)

Cad 4: Datapath & Control Unit & Memory (Team work)

Cad 5: Synthesis of the Microprocessor and Implementation on the FPGA (Team work)

Final Project:

The topic of the final project will be chosen by the students with the approval of the instructor. Some possible project topics are listed below:

Spinning Display Implementation on FPGA

Fingerprint detection

Position sensing microcontroller for automobiles

Heating and cooling micro controller

Consumer electrocardiograph

MIDI processor for musical instruments

MPEG coder (decoder)

High precision motor controller

FM Stereo Transmitter

Speech Synthesis from Written Text

An image on a memory displayer

Audio FIR filter

Audio Spectrum Analyzer

Ping Pong Game

Image Loader

Students can choose either from one of these topics or propose their own project idea. Some projects examples implemented on the hardware that we have in our lab can be found on the following website (http://www.xess.com/ho03000.html) (Of Course you can not do the same thing).

The project is a very important part of this course, and has a number of components. Students will first work in teams to develop proposals. Once approved by the instructor, the same team will start to work on the projects. A final report will be required from each group at the end of classes. There will be oral presentations of the projects during the final period, and they will be reviewed by panels formed by the students based on technical merit and other criteria. Each student will also write an independent evaluation of each project. The final grade for each student will depend upon a number of things, including the quality of the team project, the level of participation in the project and panel discussions of other projects, and the quality of the final project report. Further details or changes will be available later.

Computer Resources:

BETA research laboratory will be used to develop, run and test VHDL codes for the assignments and the project. Mentor Graphics Package (Design Architect, IC, Modelsim, Leonardo and QuickSim) installed in the workstations at BETA will be used for the simulation and synthesis of the VHDL code. Every student will have an account on the workstations. Details for the account setup and instructions to use the workstations will be provided later.

You can also use the Xilinx ISE (Integrated Synthesis Environment) WebPACK CAD tool to enter, simulate, and implement your design. These are already installed in the PCs of our laboratories but they can also be downloaded for free from the website (http://www.xilinx.com/ise/logic_design_prod/webpack.htm).

We have XSA-200 boards (http://www.xess.com/prod034.php3 from Xess corporation, http://www.xess.com ) in our labs. They have  200-Kgate XILINX Spartan-II FPGAs in a 256-pin BGA packages (XC2S200-5FG256). The small XSA-200 board holds the Xilinx FPGA chip among other things. The extender board XST-3 serves as a carrier for the XSA-200 and provides additional resources such as switches, indicators, etc. Furthermore, it houses additional space for mounting a prototyping breadboard. The XSA-200 is stacked on top of the Xstend Board so that one integrated board is seen.

Grading Policy:

             Course grades will be assigned according to the following grading formula.  Please note that this formula is tentative; students will be informed of any major changes.

CAD Assignments................................. 65% (5+10+10+15+25)

Final Project:......................................... 35% (3+12+10+10)

             In most cases students will be made aware of the basic statistics (mean, median, and standard deviation) for each assignment.

EE540 Advanced Digital Design-VHDL & FPGA

BogazIcI UnIversIty

Department of ElectrICal & ELECTRONIC EngINEERING

Course Outline

(Tentative)

Mo.

Date

Material Covered

Assign.

Comments

Feb.

20

Digital System Design

 

 

 

22

Digital System Design

 

 

 

27

Digital System Design

 

 

Mar.

1

Basics of VHDL

 

 

 

6

Basics of VHDL

 

 

 

8

Basics of VHDL

 

 

 

13

Structural description of hardware in VHDL

CAD#1

 

 

15

Structural description of hardware in VHDL

 

 

 

20

Structural description of hardware in VHDL

 

 

 

22

Design organization and parameterization

CAD#2

 

 

27

Design organization and parameterization

 

Project proposals

 

29

Utilities for high level description

 

 

Apr.

3

Utilities for high level description

 

Projects start

 

5

Dataflow description of hardware in VHDL

 

 

 

10

Dataflow description of hardware in VHDL

CAD#3

 

 

12

Dataflow description of hardware in VHDL

 

 

 

17

Behavioral description of hardware in VHDL

 

 

 

19

Behavioral description of hardware in VHDL

 

 

 

24

Behavioral description of hardware in VHDL

CAD#4

 

 

26

CPU modeling and design

 

 

May

1

Spring Break

 

 

 

3

Spring Break

 

 

 

8

CPU modeling and design

CAD#5

 

 

10

Synthesis of VHDL

 

 

 

15

Synthesis of VHDL

 

 

 

17

Synthesis of VHDL

 

 

 

22

Implementation of VHDL designs using FPGA kits

 

 

 

24

Implementation of VHDL designs using FPGA kits

 

 

May

25

End of classes

Project reports due

 

 

 

 

 

May 28th-June 6th Project Presentations